DocumentCode :
3274586
Title :
Stacked-chip packaging: electrical, mechanical, and thermal challenges
Author :
Awad, Elie ; Ding, Hanyi ; Graf, Richard S. ; Maloney, J.J.
Author_Institution :
IBM Microeletronics, Essex Junction, VT, USA
Volume :
2
fYear :
2004
fDate :
1-4 June 2004
Firstpage :
1608
Abstract :
A stacked-chip package offers many benefits, including improved electrical performance (shorter chip-to-chip interconnects), reduced printed circuit board (PCB) area, reduced weight, reduced cost when compared to a multi-package solution, and efficient integration of dissimilar integrated circuit (IC) technologies. The trade-offs to these improvements are the complex electrical, mechanical, and thermal challenges associated with stacked-chip packaging. These challenges put new demands on modeling and analysis capabilities. This paper describes these challenges and how modeling and simulation are used during package design to overcome them while improving overall module performance and reducing the qualification time and overall time to market.
Keywords :
chip scale packaging; microassembling; temperature distribution; thermal management (packaging); thermal stresses; die-to-die thermal interaction; die-to-package thermal interaction; electrical challenges; maximum junction temperature; mechanical challenges; modeling; module performance; overall time to market; package design; parasitic models; qualification time; simulation; stacked-chip package; temperature distribution; thermal challenges; Application specific integrated circuits; Assembly; Cost function; Integrated circuit interconnections; Integrated circuit noise; Integrated circuit packaging; Qualifications; Silicon; Stress; Time to market;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference, 2004. Proceedings. 54th
Print_ISBN :
0-7803-8365-6
Type :
conf
DOI :
10.1109/ECTC.2004.1320330
Filename :
1320330
Link To Document :
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