DocumentCode :
3276642
Title :
A floorplan-aware interactive tool flow for NoC design and synthesis
Author :
Reza Kakoee, Mohammad ; Angiolin, Federico ; Murali, Srinivasan ; Pullini, Antonio ; Seiculescu, Ciprian ; Benini, Luca
Author_Institution :
DEIS, Univ. of Bologna, Bologna, Italy
fYear :
2009
fDate :
9-11 Sept. 2009
Firstpage :
379
Lastpage :
382
Abstract :
In this paper we present a floorplan-aware toolchain for NoC design and synthesis integrated with a graphical front-end. The resulting design methodology is highly automated yet entails rich interaction with the user, spanning across traffic flow specification, topology synthesis and physical floorplanning, with back-annotation capabilities and opportunities for incremental design. We exploit the proposed tool to implement some NoC-based case studies. We show that not only a great amount of time and effort can be saved thanks to the easy-to-use proposed environment, but also that the quality of the final netlist improves due to the optimizations unlocked by the early-stage interaction among the designer and the proposed toolchain.
Keywords :
circuit layout; interactive systems; network synthesis; network topology; network-on-chip; NoC design; NoC synthesis; floorplan-aware interactive tool; floorplan-aware toolchain; physical floorplanning; topology synthesis; traffic flow specification; Bandwidth; Design methodology; Design optimization; Graphical user interfaces; Large scale integration; Network synthesis; Network topology; Network-on-a-chip; Process design; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location :
Belfast
Print_ISBN :
978-1-4244-4940-8
Electronic_ISBN :
978-1-4244-4941-5
Type :
conf
DOI :
10.1109/SOCCON.2009.5398016
Filename :
5398016
Link To Document :
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