Title :
SPICE versus STA tools: Challenges and tips for better correlation
Author :
Motassadeq, TariqEL ; Sarathi, Vijay ; Thameem, Syed ; Nijam, Mohamed
Author_Institution :
Dubai Circuit Design, Dubai, United Arab Emirates
Abstract :
With shrinking geometries and increasing complexity of the designs, the use of SPICE simulator (SPICE) is a must to perform accurate timing analysis of the critical paths. This also improves the signoff confidence of the design. However, in this process designers may discover a miscorrelation between static timing analysis (STA) and SPICE. There are articles that provide in-depth descriptions of STA-SPICE correlation flows. This paper addresses key challenges and offers useful tips in timing and noise correlation.
Keywords :
SPICE; timing; SPICE simulator; noise correlation; static timing analysis; timing correlation; Analytical models; Circuit synthesis; Delay effects; Geometry; Libraries; Noise measurement; Pins; SPICE; Solid modeling; Timing;
Conference_Titel :
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location :
Belfast
Print_ISBN :
978-1-4244-4940-8
Electronic_ISBN :
978-1-4244-4941-5
DOI :
10.1109/SOCCON.2009.5398029
