DocumentCode
3277446
Title
Improved write margin 6T-SRAM for low supply voltage applications
Author
Moradi, Farshad ; Wisland, Dag T. ; Mahmoodi, Hamid ; Tuan Vu Cao
Author_Institution
Dept. of Inf., Univ. of Oslo, Oslo, Norway
fYear
2009
fDate
9-11 Sept. 2009
Firstpage
223
Lastpage
226
Abstract
In this paper a new technique to increase the write margin of 6T-SRAM cell is proposed. Using this technique the area of subthreshold SRAM cell is reduced and also the Write cycle is improved significantly with a lower area overhead. In this technique, PMOS stacked network is used to evaluate the write cycle. Based on behavior of devices in 65 nm for weak inversion operation, this technique is proposed to decrease area overhead of 6T-SRAM in subthreshold region.
Keywords
SRAM chips; low-power electronics; 6T-SRAM cell; PMOS stacked network; size 65 nm; write margin; CMOS technology; Circuit simulation; Fluctuations; Informatics; Leakage current; Low voltage; MOS devices; MOSFETs; Nanoelectronics; Random access memory; 65nm; SRAM; Sub-threshold;
fLanguage
English
Publisher
ieee
Conference_Titel
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location
Belfast
Print_ISBN
978-1-4244-4940-8
Electronic_ISBN
978-1-4244-4941-5
Type
conf
DOI
10.1109/SOCCON.2009.5398053
Filename
5398053
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