Title :
System-level modeling and validation increase design productivity and save errors
Author_Institution :
Mentor Graphics, Wilsonville
Abstract :
As the complexity of system on chip (SoC) devices rises to include scores, in some cases hundreds, of distinct blocks, system validation becomes a critical concern. A variety of techniques have emerged to help designers verify that individual blocks of a device meet performance specification. But what about functional intent? Are performance goals achieved? In this paper, we make the case for high-level system validation before RTL implementation, and present a flow to approach this increasingly essential task.
Keywords :
integrated circuit design; integrated circuit modelling; system-on-chip; RTL implementation; SoC; design productivity; high-level system validation; performance specification; system validation; system-level modeling; system-on-chip; Graphics; Hardware; Performance analysis; Performance gain; Power system modeling; Productivity; Software performance; Software standards; System-level design; Traffic control;
Conference_Titel :
System-on-Chip, 2005. Proceedings. 2005 International Symposium on
Conference_Location :
Tampere
Print_ISBN :
0-7803-9294-9
DOI :
10.1109/ISSOC.2005.1595631