DocumentCode
3277879
Title
Exploiting the Area X Performance Trade-off with Code Compression
Author
Netto, E. Wanderley ; Billo, E. ; Azevedo, R.
Author_Institution
GEINF, Natal
fYear
2005
fDate
17-17 Nov. 2005
Firstpage
42
Lastpage
45
Abstract
Code compression has been shown to be efficient in code size reduction and, recently in performance improvement. In this paper we use a compression method, the ComPacket, which has a very fast decompressor in hardware, to compress selective regions of the code (the inner-loops) to improve performance and in the complementary regions we use the instruction based compression (IBC) method to sustain the code size reduction both at the same time. Using the Leon (SPARC v8) platform and benchmarks from Mediabench and MiBench suites we reached 29% of memory area reduction, on average, and a speed-up of 1.8 simultaneously.
Keywords
cache storage; instruction sets; microprocessor chips; reduced instruction set computing; ComPacket; Leon platform; Mediabench; MiBench suites; RISC processors; SPARC v8; code compression; code size reduction; instruction based compression; memory area reduction; Degradation; Delay; Dictionaries; Encoding; Engines; Hardware; Memory management; Reduced instruction set computing; Robustness; Surges;
fLanguage
English
Publisher
ieee
Conference_Titel
System-on-Chip, 2005. Proceedings. 2005 International Symposium on
Conference_Location
Tampere
Print_ISBN
0-7803-9294-9
Type
conf
DOI
10.1109/ISSOC.2005.1595640
Filename
1595640
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