Title :
Dual-band CDR using a half-rate linear phase detector
Author :
Hwang, Chorng-Sii ; Cho, Chun-Yung ; Chen, Chung-Chun ; Tsao, Hen-Wai
Author_Institution :
Dept. of Electr. Eng., Nat. Yunlin Univ. of Sci. & Tech., Yunlin, Taiwan
Abstract :
This paper describes a dual-band clock and data recovery circuit using a new half-rate linear phase detector. With the proposed sampling scheme, the phase detector produces UP/DN signals with equal pulsewidth and thus eliminates the demand of current scaling in the charge pump. The test chip fabricated by CMOS 0.18 ¿m 1P6M process can operate at 2.7 and 1.62 Gbps which satisfies the DisplayPort standard. It can recover the NRZ data of a (27-1) PRBS with a bit error rate less than 10-12. The chip core occupies an area of 0.36 mm2. The power consumption is 50 mW at 2.7 Gbps with a 1.8 V supply voltage.
Keywords :
CMOS integrated circuits; charge pump circuits; error statistics; integrated circuit manufacture; integrated circuit testing; phase detectors; synchronisation; 1P6M process; CMOS; DisplayPort standard; bit error rate; bit rate 1.62 Gbit/s; bit rate 2.7 Gbit/s; charge pump; clock recovery circuit; current scaling; data recovery circuit; half-rate linear phase detector; power 50 mW; size 0.18 mum; voltage 1.8 V; CMOS process; Charge pumps; Circuit testing; Clocks; Detectors; Dual band; Optical signal processing; Phase detection; Signal sampling; Space vector pulse width modulation;
Conference_Titel :
SOC Conference, 2009. SOCC 2009. IEEE International
Conference_Location :
Belfast
Print_ISBN :
978-1-4244-4940-8
Electronic_ISBN :
978-1-4244-4941-5
DOI :
10.1109/SOCCON.2009.5398097
