DocumentCode :
3278637
Title :
A test strategy for nanoscale wafer level packaged circuits
Author :
Keezer, D.C. ; Davis, J.S. ; Ang, S. ; Rotaru, M.
Author_Institution :
Georgia Inst. of Technol., Atlanta, GA, USA
fYear :
2002
fDate :
10-12 Dec. 2002
Firstpage :
175
Lastpage :
179
Abstract :
This paper presents a strategy for testing future generations of wafer-level packaged logic devices that have nanoscale I/O structures. The strategy assumes that the devices incorporate built-in self test (BIST) features so that only a subset of the functional I/O needs to be directly accessed during testing. A miniature tester is described that provides test control, pattern sequencing, and critical timing for the test. An interposer is used for electro-mechanical connection between the miniature tester and the device I/O nanostructures. Prototypes of the miniature tester are presented that demonstrate the fundamental ability to control logic transitions with 20ps or better accuracy, as is required to meet the test needs for 5 Gbps signals. A complete 5 Gbps miniature tester is under development using the results obtained in the prototyping phases of the project.
Keywords :
built-in self test; integrated circuit packaging; integrated circuit testing; timing; 5 Gbit/s; BIST; critical timing; electro-mechanical connection; logic transitions; nanoscale I/O structures; nanoscale wafer level packaged circuits; pattern sequencing; prototyping; test control; Automatic testing; Built-in self-test; Circuit testing; Logic devices; Logic testing; Nanoscale devices; Packaging; Prototypes; Timing; Wafer scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics Packaging Technology Conference, 2002. 4th
Print_ISBN :
0-7803-7435-5
Type :
conf
DOI :
10.1109/EPTC.2002.1185663
Filename :
1185663
Link To Document :
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