A miniature serial-data SIMD architecture

This paper proposes a new serial-data SIMD architecture for area-critical applications. It is shown that the use of a number of interleaved data in a serial-data processing element (PE), allows for the formulation of a PE based on shift registers. Furthermore, the shift registers can be implemented as a set of identical serial access memories with low-activity control. Regularity in layout and in control can be preserved also for multiplexing to and demultiplexing from the PE, as these interfaces are based on two serial access memories which are identical to the shift registers. A serial/parallel multiplier adjusted to interleaving is provided as an example. For a fixed throughput, e.g. a SIMD architecture based on 64 multipliers, each of which operates on eight concurrent and bit-interleaved data streams, roughly would occupy only 25% of the area of 512 conventional multipliers