Title :
Design and Implementation of a DDR3-based Memory Controller
Author :
Pan Guoteng ; Luo Li ; Ou Guodong ; Dou Qiang ; Xie Lunguo
Abstract :
Memory performance has become the major bottleneck to improve the overall performance of the computer system. DDR3 SDRAM is a new generation of memory technology standard introduced by JEDEC, support multibank in parallel and open-page technology. On the basis of in-depth study of DDR3 timing specification, design a DDR3-based memory controller. Memory access control module is the most key component of the memory controller. Using the stream test bench evaluate the performance, experimental results show that the memory controller of our design can correctly schedule memory access transaction, improve memory bandwidth.
Keywords :
DRAM chips; memory architecture; DDR3 SDRAM; DDR3 based memory controller; DDR3 timing specification; JEDEC; computer system; memory access control module; memory access transaction; memory bandwidth; memory performance; memory technology standard; multibank; open page technology; parallel; stream test bench; Access control; Bandwidth; Built-in self-test; Memory management; Registers; SDRAM; Timing; DDR3 SDRAM; memory access scheduling; memory bandwidth; memory controller;
Conference_Titel :
Intelligent System Design and Engineering Applications (ISDEA), 2013 Third International Conference on
Conference_Location :
Hong Kong
Print_ISBN :
978-1-4673-4893-5
DOI :
10.1109/ISDEA.2012.132