Title :
A 32 bit RISC processor with concurrent error detection
Author :
Maamar, A. ; Russell, G.
Author_Institution :
Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
Abstract :
The paper describes the design and implementation of a 32-bit RISC processor with a concurrent error detection capability. The CED scheme uses Dong´s (1982) code where the error detection capability depends upon the number of check bits used and not upon the number of data bits, hence can be made application specific. The equations used for check symbol prediction of both arithmetic and logical functions are outlined and its incorporation in a 32 bit fault-tolerant RISC processor described
Keywords :
digital arithmetic; error detection; fault tolerant computing; microprocessor chips; reduced instruction set computing; 32 bit; 32 bit fault-tolerant RISC processor; arithmetic functions; check bits; check symbol prediction; concurrent error detection; logical functions; Arithmetic; Circuit faults; Circuit testing; Design engineering; Equations; Fault tolerance; Hardware; Reduced instruction set computing; Redundancy; Very large scale integration;
Conference_Titel :
Euromicro Conference, 1998. Proceedings. 24th
Conference_Location :
Vasteras
Print_ISBN :
0-8186-8646-4
DOI :
10.1109/EURMIC.1998.711840
