DocumentCode
3280231
Title
CPI challenges in advanced Si technology nodes
Author
Liu, C.S. ; Pu, H.P. ; Chen, Christopher S. ; Tsai, H.Y. ; Lee, C.H. ; Lii, M.J. ; Yu, Doug C. H.
Author_Institution
R&D, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
fYear
2013
fDate
13-15 June 2013
Firstpage
1
Lastpage
3
Abstract
The key chip-package-integration (CPI) challenges and solutions in the packaging and assembly of advanced Si technology nodes are reported. The key challenge of CPI due to the use of fragile extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL) layer has been resolved by optimizing bump structure and materials set including both the organic substrate and solder materials, along with process improvements for both Pb-free solder and Cu bump in flip chip packages.
Keywords
assembling; dielectric materials; elemental semiconductors; flip-chip devices; integrated circuit packaging; silicon; solders; BEOL layer; CPI; ELK; Si; assembly; back-end-of-line layer; bump structure optimization; chip-package-integration; flip chip packaging; fragile extreme low-k dielectric material; organic substrate; solder material; Flip-chip devices; Packaging; Reliability; Silicon; Stress; Substrates;
fLanguage
English
Publisher
ieee
Conference_Titel
Interconnect Technology Conference (IITC), 2013 IEEE International
Conference_Location
Kyoto
Print_ISBN
978-1-4799-0438-9
Type
conf
DOI
10.1109/IITC.2013.6615559
Filename
6615559
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