Development of a test environment for pre- and post-synthesis verification of correct VHDL description of core processor systems

For the development of both new and legacy core processor systems, the development of an automated pre-synthesis simulation environment which can be used to verify correct hardware description language (HDL) description of the processor is most critical and is the primary subject of the paper. It is most critical in that first, it will help assure that the HDL described processor will correctly execute its assembly language instruction set. Secondly, automation of the pre-synthesis simulation environment will significantly reduce the time required for pre-synthesis design capture verification. Thirdly, parts of the automated pre-synthesis simulation environment can be used for post-synthesis prototype testing. The paper first specifically describes an automated pre-synthesis simulation environment developed to test and verify correct VHDL description of a complex legacy core processor, a Zilog Z8001 processor. Secondly, unique test programs are written for the processor, each of which tests portions of the VHDL code written to describe the processor. The same methodology and procedures can be used to create an automated pre-synthesis simulation test environment for other new and legacy core processor designs. A method of verifying correct synthesis of a prototype of a legacy or new processor system is also presented