Abstract :
The next generations of CMOS will soon be providing capacity to regularly implement 100M transistor ASIC/ASSP devices. As such devices will be capable of embedding the entire system functionality of many of today´s end-products they will truly be Systems-in Silicon (SIS). As alloys of hardware and software delivering end-product functionality, SiS will be much more than just complex logic-devices and their design process will need to reflect this. It will be much more capable than the linear extension of current logic-based approaches. The author believes that it is possible to develop a generic `map´ of the system-level development process. And that such map can be used to identify the methods and interfaces as well as guide the development and integration of tools and tool-chains for SiS. Accordingly, this paper attempts to quantify some of this, examining the general (Integrated) nature of systems and their development, and transferring lessons to the emerging SiS need. Further, identifying some important features of such a map, and illustrating its value on the organisation of today´s business and the deployment of tools in preparation for SiS
Keywords :
high level synthesis; CMOS; SiS; component based systems-in-silicon; design process; integrated development model; system-level development process; Application specific integrated circuits; Bridges; CMOS process; Geometry; Intellectual property; Process design; Semiconductor device modeling; Silicon; Tires; Virtual colonoscopy;
