DocumentCode
3283307
Title
A VLSI architecture for cellular automata based parallel data compression
Author
Bhattacharjee, S. ; Bhattacharya, J. ; Raghavendra, U. ; Saha, D. ; Chaudhuri, P. Pal
Author_Institution
Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., Kharagpur, India
fYear
1996
fDate
3-6 Jan 1996
Firstpage
270
Lastpage
275
Abstract
Analytical study of three neighbourhood two state per cell Cellular Automata (CA) behaviour is a comparatively recent phenomenon. A wide variety of applications have been developed utilizing the elegant structure of group CA. In this paper some of the characterizations of the state transition behaviour of non-group CA are reported. These results are subsequently utilized to develop an efficient parallel scheme for data compression. The experimental results confirms its superiority in terms of compression ratio over UNIX Compress and GZIP packages
Keywords
VLSI; cellular automata; data compression; parallel architectures; VLSI architecture; cellular automata; nongroup CA; parallel data compression; state transition; Computer architecture; Computer science; Data compression; Encoding; Matrices; Packaging; Tree graphs; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 1996. Proceedings., Ninth International Conference on
Conference_Location
Bangalore
ISSN
1063-9667
Print_ISBN
0-8186-7228-5
Type
conf
DOI
10.1109/ICVD.1996.489609
Filename
489609
Link To Document