Gate Line Edge Roughness Amplitude and Frequency Variation Effects on Intra Die MOS Device Characteristics

Random variations in manufacturing process outcomes, which are inherent to the processes, pose fundamental limitations to the die-level uniformity of the performance characteristics of nominally identical devices. Modeling based on consideration of the statistical nature of fluctuations in process outcomes becomes imperative for both product designers and process engineers at sub-65 nm technology nodes, especially when the size of the principle dimension of a device becomes comparable to the random fluctuations in physical dimensions (roughness). The inherently 3D nature of devices of this size and the interaction of field fringing and the quantum mechanical charge confinement effect further complicate device modeling