Interrupt Costs in Embedded System with Short Latency Hardware Accelerators

The current trend for handheld device is to provide the users various embedded multimedia applications. These new applications constrain architecture developers to embed dedicated hardware accelerators in order to meet the application timing requirements. However the use of dedicated monolithic hardware accelerators is onerous to achieve due to physical and economical constraints. When the multimedia applications share common functionalities, monolithic hardware accelerators could be split into smaller accelerators in order to cut down redundancy in hardware implemented functionalities and save silicon area. Nevertheless lowering the granularity of accelerator will increase synchronization calls between the main processor and the accelerators. This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.