DocumentCode
3288347
Title
Scan testing of latch arrays
Author
Hui, Michael M Y ; Nadeau-Dostie, Benoit
fYear
1992
fDate
7-9 April 1992
Firstpage
31
Lastpage
36
Abstract
A novel scan-based test method that allows latch-based arrays to be fully tested using conventional scan software tools is described. Very little support circuitry and simple modeling are required. Several useful applications of the method are described. The method was used on several production chips.<>
Keywords
boundary scan testing; logic arrays; logic testing; production testing; latch arrays; production chips; scan-based test method; software tools; Application software; Circuit testing; Combinational circuits; Flip-flops; Intelligent networks; Latches; Sequential analysis; Shift registers; Software testing; Software tools;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium, 1992. '10th Anniversary. Design, Test and Application: ASICs and Systems-on-a-Chip', Digest of Papers., 1992 IEEE
Conference_Location
Atlantic City, NJ, USA
Print_ISBN
0-7803-0623-6
Type
conf
DOI
10.1109/VTEST.1992.232720
Filename
232720
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