DocumentCode
3289403
Title
Low-Power Register File Using N-type and P-type Adiabatic Logic Circuits
Author
Li, Linfeng ; Hu, Jianping ; Yu, Lili
Author_Institution
Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China
fYear
2009
fDate
16-17 May 2009
Firstpage
342
Lastpage
345
Abstract
A 32times32 register file based on dual transmission gate adiabatic logic (DTGAL) is implemented with TSMC 0.18 mum process. The energy of all nodes with large capacitances including storage cells can be well recovered without non-adiabatic loss. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. The results show the adiabatic register file can work very well.
Keywords
circuit layout; logic circuits; logic gates; N-type adiabatic logic circuit; P-type adiabatic logic circuit; TSMC; adiabatic register file; dual transmission gate adiabatic logic; energy simulation; full-custom layouts; functional simulation; low-power register file; Capacitance; Circuit simulation; Driver circuits; Energy loss; Energy storage; Information science; Logic circuits; Logic gates; Registers; SPICE; energy recovery; low power; memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits, Communications and Systems, 2009. PACCS '09. Pacific-Asia Conference on
Conference_Location
Chengdu
Print_ISBN
978-0-7695-3614-9
Type
conf
DOI
10.1109/PACCS.2009.176
Filename
5232356
Link To Document