Implementation of optimization networks in synchronous massively parallel hardware

In this paper, implementation possibilities of a synchronous binary neural model for solving optimization problems in massively parallel hardware are studied. It is argued that synchronous, as opposed to asynchronous models are best suited to the general characteristics of massively parallel architectures. In this study the massively parallel target device is the BSP400 (brain style processor with 400 nodes). The updating of the nodes in the BSP400 is synchronous and the nodes can only process local data (i.e., activations). The synchronous models studied, introduced by Takefuji, make use of both local and global operators. The functionality of these operators with regard to the quality of the solutions is examined through software simulations. Fully digital neurocomputers such as the BSP400 offer sufficient flexibility for programming local operations on node level. The possibilities of translating the function of global operators into local operations are also studied. The aim of this study is to combine massively parallel hardware with synchronous neural network models for optimization problems in order to achieve both high speed and high quality of the solutions.