Correlated double sample design for CMOS image readout IC

Author

Jun, Gao ; Zhongjian, Chen ; Wengao, Lu ; Wentao, Cui ; Lijiu, Ji

Author_Institution

Inst. of Microelectron., Peking Univ., Beijing, China

Volume

2

fYear

2004

fDate

18-21 Oct. 2004

Firstpage

1437

Abstract

A correlated double sample (CDS) stage design is proposed for CMOS image readout IC (ROIC) in this paper. A capacitor transimpedance amplifier (CTIA) stage is used as front stage. A parasitic insensitive switch capacitor (SC) circuit is used to realize CDS on chip. This circuit also supports integration-while-read (IWR) mode, then channels low frequency noise is reduced and frame frequency is increased. A circuit based on this method is fabricated with 1.2 m CMOS technology. The simulation and measurement results are also given in this paper.

Keywords

CMOS image sensors; amplifiers; capacitors; integrated circuit design; CMOS image readout IC; capacitor transimpedance amplifier; correlated double sample design; integration-while-read; parasitic insensitive switch capacitor; CMOS integrated circuits; CMOS technology; Circuit simulation; Frequency; Integrated circuit measurements; Low-frequency noise; Semiconductor device measurement; Switched capacitor circuits; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on

Print_ISBN

0-7803-8511-X

Type

conf

DOI

10.1109/ICSICT.2004.1436861

Filename

1436861