A solution for hardware emulation of non volatile memory macrocells

More and more system verification makes use of hardware emulation techniques that allow a speed up in simulation performance of up to a thousand times. Typically, a design is composed of several parts, most of them available as RTL code, others, mainly memories, only as behavioral models. In this scenario, coemulation is necessary to verify the heterogeneous system descriptions, but this way most of the advantage of hardware emulation is lost. This paper presents a solution for modeling the analog array of a non volatile memory based on a VHDL synthesizable description. The presented approach relies on static RAMs and ROMs for which emulation models are assumed to be available. The adoption of a synthesizable model for the analog block makes possible the mapping of the entire design on the emulator thus exploiting its performance at full speed for efficient simulation sessions.