A BIST scheme for testing a multiple FPGA system

In this paper, an efficient built-in self test (BIST) scheme for testing a multiple field programmable gate array (FPGA) system is presented. We define a multiple FPGA system as a group of FPGAs on the same board or system. The proposed scheme can not only detect faults within the configurable logic blocks (CLBs) of the FPGAs being tested, but can also locate and identify the component within the CLB that is faulty. In this scheme, one of the FPGAs in the multiple FPGA system is configured as a master FPGA. The other FPGAs in the system are configured as circuit under test (CUT) and are called slave FPGAs. The master FPGA generates the testing patterns, analyzes the output responses from the slave FPGAs and controls the overall BIST mechanism. The control logic circuitry needed is mapped on the master FPGA itself and is used to configure the slave FPGAs for the different test modes. It also keeps track of the number of CLBs tested and triggers the reconfiguration process in slave FPGAs, and controls the overall BIST mechanisms. The testing scheme described in this paper is divided into two main modes: the 32*1 SRAM mode and the fast carry logic mode. Each mode requires eight subconfigurations for testing the multiple FPGA system.