DocumentCode
329118
Title
Neural network computation in a parallel multiprocessor architecture
Author
Kotilainen, Petri ; Saarinen, Jukka ; Kaski, Kimmo
Author_Institution
Microelectron. Lab., Tampere Univ. of Technol., Finland
Volume
2
fYear
1993
fDate
25-29 Oct. 1993
Firstpage
1979
Abstract
A parallel multiprocessor architecture for general-purpose neurocomputing applications is introduced. Methods to map the multilayer perceptron, Kohonen´s self-organising feature map and Kanerva´s sparse distributed memory to the suggested architecture are discussed. The mapping examples include both the forward operation and training phase of the networks. The computational performance of the architecture is estimated for these three example cases.
Keywords
optical information processing; parallel architectures; self-organising feature maps; Kanerva´s sparse distributed memory; Kohonen´s self-organising feature map; general-purpose neurocomputing; mapping examples; multilayer perceptron; neural network computation; parallel multiprocessor architecture; training phase; Communication networks; Computer architecture; Computer networks; Concurrent computing; Digital signal processors; Intelligent networks; Neural networks; Neurons; Parallel processing; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
Print_ISBN
0-7803-1421-2
Type
conf
DOI
10.1109/IJCNN.1993.717045
Filename
717045
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