Architecture and Algorithms for Syntetizable Neural Networks with On-Chip Learning

This paper presents a synthesizable programmable logic blocks architectures, describes the associated formula that makes the blocks to be generic for a backpropagation neural network (NN) with on-chip delta rule learning. The architecture proposed herein takes advantage of distinct datapaths for the forward and backward propagation stages to significantly improve the performance of the learning phase. The architecture is easily scalable and able to cope with arbitrary network sizes with the same hardware.