DocumentCode
3293134
Title
Impact of strain on the performance of high-k/metal replacement gate MOSFETs
Author
Wang, Xingsheng ; Roy, Scott ; Asenov, Asen
Author_Institution
Dept. of Electron. & Electr. Eng., Univ. of Glasgow, Glasgow
fYear
2009
fDate
18-20 March 2009
Firstpage
289
Lastpage
292
Abstract
This paper presents a simulation study of the impact of strain on scaled high performance pMOSFETs. The gate-last strain enhancement technique is employed in high-k/metal gate technology to fortify strain, and the underlying strain enhancement mechanism is studied. The strain contribution to performance improvement is differentiated from that due to the other beneficial aspects of the metal gate. Finally, the factors affecting device performance enhancement due to the scaling process are explored.
Keywords
MOSFET; high-k dielectric thin films; stress analysis; device performance enhancement; gate-last strain enhancement technique; high-k-metal replacement gate technology; scaled high performance pMOSFET; strain impact; Calibration; Capacitive sensors; Compressive stress; Doping; High K dielectric materials; High-K gate dielectrics; Laser modes; MOSFET circuits; Simulated annealing; Strain measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Ultimate Integration of Silicon, 2009. ULIS 2009. 10th International Conference on
Conference_Location
Aachen
Print_ISBN
978-1-4244-3704-7
Type
conf
DOI
10.1109/ULIS.2009.4897592
Filename
4897592
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