Reliability problems investigation during the pLEDMOS fabrication

Author

Qian, Qinsong ; Wu, Hong ; Liu, Siyang ; Sun, Weifeng ; Shi, Longxing

Author_Institution

Nat. ASIC Syst. Eng. Res. Center, Southeast Univ., Nanjing, China

fYear

2009

fDate

6-10 July 2009

Firstpage

430

Lastpage

433

Abstract

An optimized process design of the p-type lateral extended drain MOS transistor (pLED-MOS) for PDP driver ICs is developed. The following issues such as surface damage, parasitic BJT punch-through phenomenon, impurity segregation effect and creep behavior of the breakdown voltage are investigated. Various approaches are therefore sought in order to solve these reliability problems by optimizing the process and device architecture. The methods have been verified by the TCAD simulation and experimental results.

Keywords

MOSFET; bipolar transistors; electric breakdown; integrated circuit reliability; PDP driver IC; TCAD simulation; breakdown voltage; creep behavior; impurity segregation effect; p-type lateral extended drain MOS transistor; pLEDMOS fabrication; parasitic BJT punch-through phenomenon; reliability problems investigation; surface damage; Creep; Design optimization; Diffusion processes; Fabrication; Implants; Impurities; Mass production; Process design; Temperature; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Physical and Failure Analysis of Integrated Circuits, 2009. IPFA 2009. 16th IEEE International Symposium on the

Conference_Location

Suzhou, Jiangsu

ISSN

1946-1542

Print_ISBN

978-1-4244-3911-9

Electronic_ISBN

1946-1542

Type

conf

DOI

10.1109/IPFA.2009.5232616

Filename

5232616