Testable and fault tolerant design for FFT networks

Author

Li, Jin-Fu ; Wu, Cheng-Wen

Author_Institution

Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan

fYear

1999

fDate

36465

Firstpage

201

Lastpage

209

Abstract

We propose a novel C-testable technique for the fast-Fourier-transform (FFT) networks. Only 18 test patterns are required to achieve 100% coverage of combinational single cell faults and interconnect stuck-at faults for the FFT network. A fault tolerant design for the FFT network also has been proposed. Compared with previous results, our approach has higher reliability and lower hardware overhead-only three spare bit-level cells are needed for repairing a faulty row in the multiply-subtract-add (MSA) module, and special cell design is not required to implement the reconfiguration scheme. The hardware overhead is low-about 4% for 16-bit numbers regardless of the FFT network size

Keywords

VLSI; cellular arrays; design for testability; digital signal processing chips; fast Fourier transforms; fault tolerant computing; integrated circuit design; integrated circuit reliability; integrated circuit testing; logic arrays; logic design; reconfigurable architectures; 16 bit; C-testable technique; DFT; DSP chip; FFT networks; combinational single cell faults; fast Fourier transform networks; fault tolerant design; hardware overhead reduction; interconnect stuck-at faults; multiply-subtract-add module; reconfiguration scheme; reliability improvement; test patterns; testable design; Character generation; Circuit faults; Circuit testing; Fault detection; Fault tolerance; Hardware; Integrated circuit interconnections; Network-on-a-chip; System-on-a-chip; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Defect and Fault Tolerance in VLSI Systems, 1999. DFT '99. International Symposium on

Conference_Location

Albuquerque, NM

ISSN

1550-5774

Print_ISBN

0-7695-0325-x

Type

conf

DOI

10.1109/DFTVS.1999.802886

Filename

802886