DocumentCode
3295653
Title
VLSI architecture for MQ coder in JPEG2000
Author
Ramulu, G. ; Kumar, A.T.R. ; Rao, Aravinda S. ; Chandra, Shekhar S. ; Gopal, M.M.
Author_Institution
Dept. of ECE, Aurora´s Technol. & Res. Inst. (ATRI), Hyderabad, India
fYear
2012
fDate
5-7 Dec. 2012
Firstpage
106
Lastpage
110
Abstract
The embedded block coding with optimized truncation (EBCOT) is a key algorithm in JPEG2000 image compression standard. The matrix quantizer (MQ) coder used in this algorithm restricts throughput of the EBCOT because feedback loop operations are iterative. To overcome this we use phase shift clocks to update registers used in MQ coder. The proposed architecture is implemented on Virtex-5 Xilinx FPGA.
Keywords
VLSI; block codes; clocks; data compression; field programmable gate arrays; image coding; EBCOT; JPEG2000 image compression standard; MQ coder; VLSI architecture; Virtex-5 Xilinx FPGA; embedded block coding with optimized truncation; feedback loop operations; matrix quantizer coder; phase shift clocks; Clocks; Encoding; Image coding; Indexes; Registers; Transform coding; Very large scale integration; EBCOT; FPGA; MQ coder;
fLanguage
English
Publisher
ieee
Conference_Titel
Microelectronics and Electronics (PrimeAsia), 2012 Asia Pacific Conference on Postgraduate Research in
Conference_Location
Hyderabad
ISSN
2159-2144
Print_ISBN
978-1-4673-5065-5
Type
conf
DOI
10.1109/PrimeAsia.2012.6458636
Filename
6458636
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