Title :
A 0.58-1 Gb/s CMOS data recovery circuit using a synchronous digital phase aligner
Author :
Cheung, T.S. ; Lee, B.C.
Author_Institution :
Dept. of Network Core Technol., ETRI, Daejon, South Korea
Abstract :
A data recovery circuit using a newly proposed synchronous digital phase aligner is realized for multi-link applications. The proposed circuit is implemented with 0.35 μm CMOS process technology. The experimental results show that the proposed circuit successfully recovers incoming 0.58-1 Gb/s of 231-1 pseudo random bit sequence with less than 10-14 of bit error rate.
Keywords :
CMOS digital integrated circuits; data communication equipment; digital communication; error statistics; phase comparators; synchronisation; timing; transceivers; 0.35 micron; 0.58 to 1 Gbit/s; BER; CMOS data recovery circuit; bit error rate; double-poly four-metal n-well CMOS process; minimum jitter; multi-link applications; pseudo random bit sequence; synchronous digital phase aligner; wander tolerance; CMOS digital integrated circuits; CMOS process; CMOS technology; Clocks; Jitter; Metastasis; Phase locked loops; Timing; Transceivers; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on
Print_ISBN :
0-7803-7523-8
DOI :
10.1109/MWSCAS.2002.1187054
