Statistical Variations of Interconnect Parasitics: Extraction and Circuit Simulation

With an increasing influence of parasitic interconnect properties on the circuit performance, one also sees an increasing necessity to appropriately model the corresponding fluctuations induced by unavoidable random process variations, and to include them in subsequent circuit simulations. The paper discusses an efficient approach that addresses this problem using a semi-analytic approximation. It is based on an appropriate linearization scheme which allows one to systematically analyze the fluctuations of the parasitic capacitance and resistance values of given layout configurations. After a short sketch of the basic approach, we first discuss how the method is used to systematically analyze random variations of interconnect properties of simple representative two-dimensional interconnect models for long bus line configurations. In the second part of the paper we then sketch a 3D flow implementation for a full interconnect-parasitics variation-extraction for real industrial layouts