A novel architecture for integrated CMOS wideband PLL-based frequency synthesizer

Conventional CMOS frequency synthesizers have limited tuning range. The limited tuning range make the RF front-end need special technology to meet the frequency specification of wideband communications. A new architecture for an integrated wideband phase locked loop (PLL)-based frequency synthesizer is presented. The largest achieved tuning range is dependent on the largest available power supply in a system. A method of multiple power supplies has been used to produce the large tuning range with a low voltage controlled oscillator (VCO) gain which can reduce the level of reference spurs and realize 200 kHz or 1 MHz channel bandwidth. A prototype, which is the integer-N PLL-based frequency synthesizer, is designed and simulated using the TSMC 0.18 μm CMOS RF model. The tuning range at center frequency 1.1 GHz is more than 250 MHz when the available largest power supply is 3 V.