Zeroing in on a zero-temperature coefficient point

The transconductance characteristics of MOS transistors realized in 0.18 μm CMOS technology have a zero-temperature coefficient (ZTC) bias point. The presence of this point influences performance of both analog and digital circuits. The offset voltage drift in a source-coupled differential pair strongly increases, if the transistor drain currents are equal to the bias currents of ZTC point. It is also impossible to find the drain voltage optimizing the temperature stability of propagation delay in digital circuits. One has to divide the digital circuits in two types. In the first type (CPU circuits) the optimal drain voltage is equal to ZTC bias point voltage of n-channel transistors, in the second case (SRAM circuits) the optimal drain voltage is equal to the absolute value of the ZTC bias point voltage of p-channel transistors.