Shield-based on-wafer CMOS test fixture employing polysilicon shield plane

An on-wafer CMOS test fixture employing a grounded polysilicon shield plane is studied in this work. The fabricated polyshielded test fixture is measured and typical parasitic components are extracted. The results are compared to metal-shielded and unshielded test fixture experimental data. In the case of demonstrated fixtures, the polysilicon-based test fixture has 48% lower parallel parasitic signal lead capacitance than a similar metal-shielded test fixture. Moreover, the polysilicon shield does not compromise the isolation between test fixture signal ports. The proposed shielding strategy can reduce the on-wafer measurement uncertainties induced by vertical process tolerances. The test fixtures were fabricated using AMS 4-metal 0.35 μm CMOS process.