DocumentCode :
3299798
Title :
A process variation tolerant technique for sub-70nm latches and flip-flops
Author :
Hansson, Martin ; Alvandpour, Atila ; Hsu, Steven K. ; Krishnamurthy, Ram K.
Author_Institution :
Dept. of Electr. Eng., Linkoping Univ., Sweden
fYear :
2005
fDate :
21-22 Nov. 2005
Firstpage :
149
Lastpage :
152
Abstract :
This paper describes a sub-70nm circuit technique that compensates the impact of the increasingly large process variations on latches and flip-flops. In contrast to the traditional design for worst-case process corners, we utilize a variable keeper circuit that preserves the robustness of storage nodes across the process corners, without degrading the overall chip performance. Power and delay improvements of 7% and 12% respectively have been observed for wide static MUX-latch circuits in a 65nm CMOS technology. Moreover, the proposed technique enables functional flip-flops with weak uninterrupted keepers leading to over 9% clock power reduction.
Keywords :
CMOS logic circuits; flip-flops; 70 nm; CMOS technology; flip-flops; latches; process corners; process variation tolerant technique; static MUX-latch circuits; storage nodes; variable keeper circuit; CMOS process; CMOS technology; Circuit testing; Degradation; Delay; Flip-flops; Latches; Leakage current; MOS devices; Robustness;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
NORCHIP Conference, 2005. 23rd
Print_ISBN :
1-4244-0064-3
Type :
conf
DOI :
10.1109/NORCHP.2005.1597011
Filename :
1597011
Link To Document :
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