DocumentCode :
3300126
Title :
Multiply-add fused RISC architectures for DSP applications
Author :
Panneerselvam, G. ; Nowrouzian, B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Volume :
1
fYear :
1993
fDate :
19-21 May 1993
Firstpage :
108
Abstract :
The development of a fixed-point bit-parallel multiply-add fused (MAF) architecture together with a corresponding VLSI implementation is presented. The proposed MAF implementation employs 1.2μ CMOS technology. This MAF implementation finds a variety of practical applications in high-speed real-time digital signal processing. The MAF implementation employs a parallel modified Booth multiplier incorporating an array of carry-save adders for the addition of the intermediate partial products, and a hardware efficient carry-skip adder for carry propagation. The performance characteristics of the MAF implementation have been successfully verified by an HSPICE simulation at speeds of up to 100 MHz
Keywords :
CMOS logic circuits; SPICE; VLSI; adders; carry logic; digital arithmetic; digital signal processing chips; logic arrays; multiplying circuits; parallel architectures; performance evaluation; real-time systems; reduced instruction set computing; CMOS technology; HSPICE simulation; RISC architectures; The performance characteristics; VLSI implementation; carry-save adders; carry-skip adder; high-speed real-time digital signal processing; multiply-add fused architecture; parallel modified Booth multiplier; Adders; Application software; CMOS technology; Computer architecture; Digital signal processing; Digital signal processing chips; Pipelines; Reduced instruction set computing; Roundoff errors; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications, Computers and Signal Processing, 1993., IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-7803-0971-5
Type :
conf
DOI :
10.1109/PACRIM.1993.407210
Filename :
407210
Link To Document :
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