Capacitive crosstalk effects on on-chip interconnect latencies and data-rates

We investigate how crosstalk affects latency, data-rate, and power dissipation for on-chip global interconnects in a 6-layer 0.18μm CMOS process. A simplified analytical interconnect description is compared to circuit simulations of a field solver extracted wire model. We show how repeater insertion can be utilized to achieve wave pipelining, which pushes maximum data-rate beyond the classical limit. Compared to simulations, the analytical model is pessimistic by 10% for latency, 30% for maximum data-rate, and 35% for power dissipation, highlighting the importance of avoiding too simple wire representations.