Title :
Low voltage low power CMOS four-quadrant analog multiplier for neural network applications
Author :
Colli, Gianluca ; Montecchi, F.
Author_Institution :
SGS-Thomson Microelectron., Agrate Brianza, Italy
Abstract :
A new low power CMOS four quadrant analog multiplier based on the operation of MOS transistors in linear region is presented. The simulated performances prove that it is possible to achieve an high input to supply ratio without a considerable amount of biasing current. Unlike almost all other designs of four quadrant multiplier in literature, this circuit allows a very low power dissipation (6 μW for cell) using both low biasing current (4 μA) and a 1.5 V supply. These properties make this circuit very suitable for ANN applications as a precise weighting synapse and for low power analog signal processing for portable applications. The circuit achieves an high linearity (less than 40 dB of Vina/b=1.5 Vpp@200 kHz) and a small area occupied (94 μm×88 μm with bias section included)
Keywords :
CMOS analogue integrated circuits; analogue multipliers; neural chips; 1.5 V; 200 kHz; 4 muA; 6 muW; ANN applications; CMOS four-quadrant analog multiplier; MOS transistor linear region; analog signal processing; low power operation; low voltage operation; neural network applications; portable applications; precise weighting synapse; Adaptive signal processing; Artificial neural networks; CMOS technology; Circuits; Frequency; Linearity; Low voltage; MOS devices; Neural networks; Power dissipation;
Conference_Titel :
Circuits and Systems, 1996. ISCAS '96., Connecting the World., 1996 IEEE International Symposium on
Conference_Location :
Atlanta, GA
Print_ISBN :
0-7803-3073-0
DOI :
10.1109/ISCAS.1996.539993