Optimised decimation stages with lattice wave digital filters for a flexible digital receiver architecture

In a digital receiver with broadband signal sampling, digital decimation filters are required. The signal is sampled and digitised in such an architecture by a properly designed quantiser and the decimation stages after the quantiser should be programmable to provide flexibility. In this contribution, a new architecture for the implementation of high-order, programmable decimation filters is described. Using this filter concept, the flexibility with respect to multimode capability and the degree of integration can be drastically increased. It will be shown that the use of cascaded low-order wave digital lattice filters for the lower decimation filter stages results in a number of advantages compared to standard methods. By properly selecting the number of lattice filter cells and optimising the filter coefficients, a very efficient realisation is possible in VLSI-technology. Due to the simple filter structures and since no general multiplier is needed, significant hardware reduction can be obtained compared to existing solutions.