The Hardware Interface Design In SoC with Verilog Language

With the geometry of the IC(integrated circuits) becoming smaller and smaller, more and more high-density integration, function integrated getting stronger and stronger and development cycle becoming shorter and shorter, the SoC (system-on-a-chip) design methodology based on IP-Reuse has become the main method to design IC. In order to automate IP-Reuse, tools must be created to combine parts of different communication protocol system in this design method, that is, to the interface synthesis. This paper gives us a kind of hardware interface synthesis method based on automatic FSM (finite state machine) generation, gives out such interface design based on Verilog language, and carries out simulation.