On-line error detection techniques for dependable embedded processors with high complexity

Author

Pfanz, M. ; Walther, K. ; Vierhaus, H.T.

Author_Institution

Comput. Eng. Dept., BTU, Cottbus, Germany

fYear

2001

fDate

2001

Firstpage

51

Lastpage

53

Abstract

Presents efficient techniques for concurrent error detection of processor components. It deals with concurrent check methods for complex data-path elements like FPUs or register-files. We propose a Berger code prediction unit for a multistage add-sub-FPU. Furthermore, the suitability of Berger code for register-files is discussed. As an alternative, the cross-parity observation is introduced. The applicability of these concepts was evaluated on several experimental processor designs up to double-precision pipeline processors

Keywords

automatic testing; data flow graphs; error detection codes; fault diagnosis; finite state machines; logic testing; microprocessor chips; pipeline processing; Berger code prediction unit; FPUs; complex data-path elements; component errors; concurrent check methods; concurrent error detection; control errors; control flow graph; cross-parity observation; data flow graph; double-precision pipeline processors; embedded processors; finite state machines; multistage add-sub-FPU; processor components; register-files; safety-critical systems; Buffer storage; Business continuity; Circuit faults; Circuit testing; Computer errors; Decoding; Electrical fault detection; Error correction; Fault detection; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Workshop, 2001. Proceedings. Seventh International

Conference_Location

Taormina

Print_ISBN

0-7695-1290-9

Type

conf

DOI

10.1109/OLT.2001.937818

Filename

937818