Sub-40 nm v-groove MOSFETs

Author

Appenzeller, J. ; Martel, R. ; Avouris, P. ; Knoch, J. ; Lu, Y. ; Wang, K.L. ; Scholvin, J. ; Del Alamo, J.A. ; Rice, P. ; Solomon, P.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2001

fDate

25-27 June 2001

Firstpage

95

Lastpage

96

Abstract

In a previous article, we showed that a V-groove design can be used to achieve sub-0.1 μm MOSFETs. A thick raised source/drain structure of highly n-doped silicon on top of an ultra-thin p/sup s/ilicon channel combines the advantages of low contact resistances with the suppression of short channel effects. Here, we present most recent results on V-groove MOSFETs with a source/drain separation down to L/sub g/= 6 nm exhibiting state of the art electrical characteristics. We therefore demonstrate that the V-groove MOSFET has potential for sub-40 nm operation.

Keywords

MOSFET; elemental semiconductors; etching; semiconductor doping; silicon; 36 nm; DIBL; Si:Sb; V-groove MOSFET; V-groove openings; anisotropic etch; output characteristic; scaling limits; source/drain separation; specific transconductance; Anisotropic magnetoresistance; Annealing; Contacts; Doping profiles; Electron beams; Etching; MOSFETs; Silicon; Table lookup; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Device Research Conference, 2001

Conference_Location

Notre Dame, IN, USA

Print_ISBN

0-7803-7014-7

Type

conf

DOI

10.1109/DRC.2001.937889

Filename

937889