DocumentCode

3303585

Title

A Timing Analysis Algorithm For Circuits With Level-sensitive Latches

Author

Lee, Jin-Fuw ; Tang, Donald T. ; Wong, C.K.

fYear

1994

fDate

6-10 Nov 1994

Firstpage

743

Lastpage

748

Keywords

Algorithm design and analysis; Circuit analysis; Clocks; Constraint optimization; Delay; Flip-flops; Job shop scheduling; Latches; Logic design; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1994., IEEE/ACM International Conference on

ISSN

1063-6757

Print_ISBN

0-8186-3010-8

Type

conf

DOI

10.1109/ICCAD.1994.629906

Filename

629906