Co-Simulation of SPICE Netlists and VHDL-AMS Models via a Simulator Interface

This paper addresses a method for simulator coupling allowing a transient time simulation of SPICE and the mixed-signal language VHDL-AMS within one simulation process. To this end, an interface between the two simulators SLSim and SMASH has been developed that links the slave simulator to the master process during runtime. Both simulator cores work independently of each other and the synchronization, which means data exchange, is done at adaptively calculated points in time. Since a mixed-signal simulator consists of an analog and a logic algorithm which are stepped independently through time, synchronization not only means data exchange between the both simulators, but also data exchange between the analog and the logic part of the VHDL-AMS simulator. Due to that, special attention has to be given to the synchronization mechanisms of the simulator interface. The functionality of the co-simulation will be shown by using examples from the field of automotive EMC simulation.