Regular flow line models for semiconductor cluster tools: A case of lot dependent process times

We develop a reduced complexity recursion for the wafer delay in each server in flow lines with wafer dependent deterministic or regular process times and demonstrate how it can serve to model lot production in semiconductor cluster tools with setups. Under certain assumptions on the process times, it is shown that the system behavior shares some similarities with the case of wafer independent process times, thereby enabling our results. Such models can be used to substantially increase the fidelity of existing fabricator simulation models, without the computational complexity of a complete step-by-step wafer, module and robot simulation. The models have been tested using data from a clustered photolithography tool in production and exhibited throughput and tool sojourn time values within 1% and 4% of the actual values, respectively.