DocumentCode
33066
Title
A Compact Analytical Model for the Drain Current of Gate-All-Around Nanowire Tunnel FET Accurate From Sub-Threshold to ON-State
Author
Vishnoi, Rajat ; Kumar, Mamidala Jagadesh
Author_Institution
Dept. of Electr. Eng., Indian Inst. of Technol. Delhi, New Delhi, India
Volume
14
Issue
2
fYear
2015
fDate
Mar-15
Firstpage
358
Lastpage
362
Abstract
We present a compact analytical model for the drain current of a gate-all-around nanowire tunneling field effect transistor. The model takes into account the effect of oxide thickness, body doping, drain voltage, and gate metal work function. The model uses a tangent line approximation method to integrate the tunneling generation rate in the source-body depletion region. The accuracy of the model is tested against three dimensional numerical simulations calibrated using experimental results. The model predicts the drain current accurately in both the on-state (strong inversion), as well as in the sub-threshold region.
Keywords
approximation theory; field effect transistors; nanowires; semiconductor device models; semiconductor doping; tunnel transistors; body doping; compact analytical model; drain current; drain voltage; gate metal work function; gate-all-around nanowire TFET; nanowire tunneling field effect transistor; oxide thickness; source-body depletion region; subthreshold region; tangent line approximation method; tunneling generation rate; Approximation methods; Electric fields; Equations; Logic gates; Mathematical model; Numerical models; Tunneling; Nanowire; OFF-state current; ON-state current; Sub-threshold slope (SS); Three dimensional (3D) modeling; Tunneling Field Effect Transistor (TFET); Tunneling field effect transistor (TFET); off-state current; on-state current; sub-threshold slope (SS); three dimensional (3-D) modeling;
fLanguage
English
Journal_Title
Nanotechnology, IEEE Transactions on
Publisher
ieee
ISSN
1536-125X
Type
jour
DOI
10.1109/TNANO.2015.2395879
Filename
7018075
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