3D multi-processors system on chip design method and Performance Analysis

We propose the three dimensional direct access multi-port buffer (3D DA-MPB) architecture for the design of 3D MP-SoCs using the wafer stack method as a fabrication technology. We design a 3D interconnection architecture template. The design method can integrate numerous processors onto a single chip. We illustrate the data transfer process between multi-port buffer storage blocks through simulations. We use the solution of master interface access to resolve the data transfer path routing problem between wafer layers. We analyze the characteristics of 3D MP-SoC and evaluate the 3D MP-SoC performance through simulations. We consider interconnect area and interconnect delay improvements, global wire length shorting, and increased throughput.