DocumentCode
3310288
Title
A Novel Signed Array Multiplier
Author
Das, Debaprasad ; Rahaman, Hafizur
Author_Institution
Sch. of VLSI Technol., Bengal Eng. & Sci. Univ., Shibpur, India
fYear
2010
fDate
20-21 June 2010
Firstpage
19
Lastpage
23
Abstract
A new architecture for the signed binary multiplier is presented in this paper. The proposed signed array multiplier has 54% area overhead as compared to Baugh Wooley multiplier but is 25% faster than the previous designs. The new design works with the operands in two’s complement format. The multiplier is based on a basic 2x2 multiplier. The final product is adjusted for negative operands. The design is implemented in TSMC 0.18um process technology node and TSPICE is used for design and simulation.
Keywords
Adders; CMOS logic circuits; Computer architecture; Design methodology; Digital arithmetic; Digital signal processing; Logic design; Registers; Signal processing algorithms; Very large scale integration; Baugh Wooley; Booth; Dadda; Multiplier; Wallace Tree;
fLanguage
English
Publisher
ieee
Conference_Titel
Advances in Computer Engineering (ACE), 2010 International Conference on
Conference_Location
Bangalore, Karnataka, India
Print_ISBN
978-1-4244-7154-6
Type
conf
DOI
10.1109/ACE.2010.29
Filename
5532881
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