Title :
IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Abstract :
The following topics were dealt with: fault-tolerant architectures; testable architectures; yield and defect models; self-checking and coding techniques; fault-tolerant techniques; reconfiguration techniques; yield enhancement; testing techniques
Keywords :
fault tolerant computing; VLSI systems; coding techniques; defect models; fault-tolerant architectures; fault-tolerant techniques; reconfiguration techniques; self-checking techniques; testable architectures; testing techniques; yield enhancement; yield models;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1994. Proceedings., The IEEE International Workshop on
Conference_Location :
Montreal, Quebec, Canada
Print_ISBN :
0-8186-6307-3
DOI :
10.1109/DFTVS.1994.630007
