Roundoff error-free tests in algorithm-based fault tolerant matrix operations on 2-D processor arrays

Assaad and Dutt [1992] proposed the hybrid checksum test method for the floating-point matrix-matrix multiplication in ABFT environment, by which the error coverage can be greatly increased. However, the threshold test in their approach is still necessary in the floating-point addition part of the matrix multiplication, and the number of error detections decreases with the increase in the dynamic range of data. Here, instead of using the threshold floating-point checksum test, we present an effective method, called the concurrent floating-point checksum (CFPC) test. The proposed CFPC test provides complete error detection/correction capabilities in floating-point additions with less time latency and hardware overhead regardless of the dynamic range of input data